1. Field of the Invention
The present invention relates to a DRAM and Method for manufacturing the DRAM, and particularly to a structure of an insulation film covering a MOS transistor (which constitutes a peripheral circuit), a cell transistor (which constitutes a memory cell), and a manufacturing method of the insulation film.
2. Description of the Related Art
In a conventional DRAM, a cell transistor comprising an N-channel MOS transistor constituting a memory cell and an N-channel MOS transistor constituting at least a part of a peripheral circuit both have an LDD-type source and drain region comprising an N.sup.- -type diffusion layer which is formed in self-alignment with the gate electrode (or word lines) and N.sup.+ -type diffusion layer which is formed in self-alignment with an insulation spacer covering a side of the gate electrode (or a word line). However, from the time of the emergence of a 64 MB-type DRAM which adopts 0.35 .mu.m design rule, an N.sup.- -type source and drain region which comprises only an N.sup.- -type diffusion layer which is self-aligned with respect to the word lines has come to be adopted in the cell transistor.
Reasons for the adoption of the N.sup.- -type source and drain region in the cell transistor can be explained as follows. An etch-back is performed with respect to an insulation film in the formation of the insulation film spacer on the side of the word lines. However, because of the damage caused by the etch-back, the deterioration of the holding characteristic becomes conspicuous in the cell transistors that are made fine by the use of a manufacturing method using a design rule on the order of 0.35 .mu.m. On the other hand, although the holding characteristic required of the N-channel MOS transistor constituting the peripheral circuit is not based on such a strict value, a drive current having a high value is required with the result that it is preferable to adopt the LDD-type source and drain region in this transistor as has been carried out in a conventional manner.
By referring to FIGS. 1A through 1D showing sectional model views illustrating steps of manufacturing a DRAM and FIGS. 2A and 2B showing plan model views of the DRAM and a sectional model view thereof and, thus giving an example of a DRAM in which the peripheral circuit such as a decoder circuit, a sense amplifier circuit or the like connected to word lines and bit lines of a memory cell, a manufacturing method of the DRAM will be explained in the case where 0.25 .mu.m (quarter micron) design rule is adopted. Incidentally, FIGS. 1A through 1D are sectional model views of the manufacturing steps at a position corresponding to line A--A of FIG. 2A. FIG. 2B is a sectional model view taken along line A--A of FIG. 2A.
This DRAM is provided on the surface of a P-type silicon substrate 201. A cell array region 251 on which a DRAM memory cell is arranged, a boundary region 252 surrounding this cell array region 251, and a peripheral circuit region 253 on which a peripheral circuit is formed are provided on the surface of the P-type silicon substrate 201. This DRAM is formed in the following manner.
In the beginning, on a device separation region of the cell array region 251 and the peripheral circuit region 253 including the boundary region 252 on the surface of the P-type silicon substrate 201, a groove having a depth of, for example, about 300 nm is formed by an anisotropic etching process. In this groove, a field insulation film 202 is filled by means of the CVD or the like. Preferably, an upper surface of the field insulation film 202 is generally flush with the surface of the P-type silicon substrate 201. On the device formation regions 203 and 204 on the surface of the P-type silicon substrate 201 surrounded by the device separation region, a gate insulation film 205 having a thickness of, for example, about 5 nm is formed. A minimum width of (the field insulation film 202 in) the boundary region 252 is, for example, about 1.2 .mu.m.
Subsequently, on an overall surface of the silicon substrate 201, an N.sup.+ -type polycrystal silicon film having a thickness of, for example, about 100 nm and a tungsten silicide film having a thickness, for example, about 100 nm are formed. This tungsten silicide film and the N.sup.+ -type polycrystal silicon film are patterned one after another by the anisotropic etching process. On the cell array region 251 and the peripheral circuit region 253, word lines 211 and a gate electrode 212 are formed respectively which are formed by the lamination of the tungsten silicide film pattern 242 on the N.sup.+ -type polycrystal silicon film pattern 241. The line width (gate width) of the word lines 211 and the gate electrode 212 are about 0.3 .mu.m and about 0.5 .mu.m respectively. The interval between adjacent word lines 211 and the interval between the word lines 211 and the field insulation film 202 are, for example, about 0.6 .mu.m respectively.
Subsequently, by means of ion implantation or the like using as a mask the field insulation film 202, the word lines 211, and the gate electrode 212, an N.sup.- -type source and drain region 214 having a junction depth of, for example, about 70 nm and an N.sup.- -type diffusion layer 215 are formed respectively on the device formation region 203 and the device formation region 204 on the surface of the P-type silicon substrate 201. As a consequence, a memory cell comprising a gate insulation film 205, word lines 211, the N.sup.- -type source and drain region 214 is completed. Here, (generally), one of the N.sup.- -type source and drain region 214 belongs to one of the word lines 211 (one memory cell) while the other of the N.sup.- -type source and drain region 214 is shared by two adjacent word lines 211 (two memory cells). The minimum interval between the gate electrode 212 and the field insulation film 202 is, for example, about 1.0 .mu.m (see FIG. 1A and FIG. 2A).
Next, a first silicon oxide film 221 having a thickness of, for example, about 130 nm is formed on the overall surface of the substrate 201 by means of a low-pressure chemical vapor deposition process (LPCVD). By means of an anisotropic etching process with a photoresist film pattern 244 covering the cell array region 251 and the boundary region 252, this silicon oxide film 221 (and the gate insulation film 205) is selectively etched back with the result that an insulation film spacer 227 (comprising the silicon oxide film 221) covering the side of the gate electrode 212 is retained and formed. The thickness of the insulation film spacer 227 is generally about 130 nm (see FIG. 1B).
By means of the ion implantation of arsenic before and after the removal of the photoresist film pattern 244 and by means of the heat treatment after the removal of the photoresist film, an N.sup.+ -type diffusion layer 229 is formed on the device formation region 204 in self-alignment with the field insulation film 202 and the insulation film spacer 227 (together with the gate electrode 212). The depth of the junction of the N.sup.+ -type diffusion layer 229 is, for example, about 200 nm. As a consequence, the N-channel MOS transistor that constitutes the peripheral circuit is completed. The source and drain region of the N-channel MOS transistor comprises an LDD type source and drain region 230 which comprises the N.sup.+ -type diffusion layer 229 and the N.sup.- -type diffusion layer 215. The thickness of the silicon oxide film 221 (insulation film spacer 227) is regulated with the depth of the N.sup.+ -type diffusion layer 229.
Subsequently, by means of an atmospheric pressure chemical vapor deposition (APCVD) process, a second silicon oxide film 231 having a thickness of, for example, about 100 nm is formed on the overall surface of the substrate 201. Furthermore, by means of the APCVD using as a material ozone (O.sub.3), TEOS (Si(OC.sub.2 H.sub.5).sub.4), TMOP (PO(OCH.sub.3).sub.3), and TMB (B(OCH.sub.3).sub.3), a BPSG film 232 having a thickness of, for example, about 200 nm is formed. Here, the reason why the APCVD process is adopted for the formation of the silicon oxide film 231, and the BPSG film 232 is that the priority is given to the productivity. The concentration of the phosphorus in the BPSG film 232 is, for example, 4.8 mol %. The concentration of boron is, for example, 10.3 mol %. At this time, the highest position on the upper surface of the BPSG film 232 is a part immediately on the word lines 211. The lowest position of the upper surface thereof is a portion immediately on the field insulation film 202 adjacent to the boundary region 252 (in the peripheral circuit region 253), and the LDD type source and drain region 230. The maximum step on the upper surface of the BPSG film 232 is about 330 nm. This value is equal to the sum of the thickness of the word lines 211 and the thickness of the first silicon oxide film 221 (see FIG. 1C and FIG. 2B).
Next, the heat treatment is carried out in the atmosphere of nitrogen, for example, at 850.degree. C. for about 10 minutes. The BPSG film 232 is reflowed and the BPSG film 233 is formed. With this reflow, the largest step on the upper surface of the BPSG film 233 is decreased to about 270 nm (see FIG. 1D).
Incidentally, on the BPSG film 232 having the thickness described above and the phosphorus concentration described above, even when the condition of the reflow is changed to, for example, a higher temperature, or a longer time, the decrease in the maximum step of the upper surface described above does not change so much. When the concentration of phosphorus is increased to a level more than the level described above, a deposition of phosphorus is generated with the result that a moisture endurance is lowered. The thickness of the BPSG film 232 is demanded by to maintain the productivity, the suppression of the overhang configuration of the BPSG film deriving from the APCVD and the suppression of the an increase in the aspect ratio of the contact hole which is formed on the interlayer insulation film (which is formed by the lamination of the BPSG film 233 on the second silicon oxide film 231). Furthermore, in the case where the thickness of the BPSG film 232 is thin in this manner, the planarization by the CMP is not favorable.
Next, a chemical amplification type and positive type photoresist film (not shown) is formed on the surface of the BPSG film 233. In agreement with the upper surface of this photoresist film in focus immediately on the word lines 211, (under the condition that an open pattern width becomes minimum at this position), an open pattern is formed on this photoresist film by means of stepper exposure using a KrF excimer laser. The anisotropic etching process is carried out with respect to the silicon oxide film using as a mask this photoresist film pattern with the result that a bit contact hole 235 which reaches the N.sup.- -type source and drain region 214 and a contact hole 236 which reaches a LDD type source and drain region 230 are formed. The bit contact hole 235 has a size on the order of 0.25 .mu.m square while the contact hole 236 has a size on the order of 0.3 .mu.m square. In the exposure described above, the reason why the open pattern width at the position described above is set to a minimum level and is prevented from becoming a maximum is that, for example, the contact hole 236 is securely formed.
After a conductive film is formed on the overall surface of the substrate, the chemical amplification type and positive type photoresist film (not shown) which covers the surface of this conductive film is formed. By focusing on the upper surface of the photoresist film immediately on the word lines 211, (under the condition that the pattern width becomes maximum at this position), the photoresist film pattern is formed by means of the stepper exposure using the KrF excimer laser. At this time, the design target width of the photoresist film pattern and the design goal minimum interval thereof are 0.216 .mu.m and 0.252 .mu.m respectively. The exposure light amount of the KrF excimer laser for this purpose is about 40 mJ. Subsequently, by using as a mask the photoresist film pattern, this conductive film is subjected to the anisotropic etching process with the result that bit line 237 and wiring 238 is formed. The bit line 237 is connected to a plurality of cell transistors via the bit contact holes 235 and are connected to at least one of the N-channel MOS transistors constituting the peripheral circuit via the contact holes 236. The bit lines 237 are used for the connection between the N-channel MOS transistors or the like constituting the peripheral circuit via the contact holes 236. The bit lines 236 vertically intersect the word lines 211 via the first silicon oxide film 221 and the interlayer insulation film comprising the BPSG film 233 and the second silicon oxide film 231 (see FIG. 2A and FIG. 2B).
Incidentally, in the exposure described above for the formation of the photoresist film for patterning the bit lines 237 and the wiring 238, the reason why the photoresist film pattern width at the position described above is set to the maximum is to avoid the short circuit of adjacent bit lines. The line width of the bit lines 237 at the portion of the bit contact holes 235 is about 0.5 .mu.m with the result that the interval between the bit lines 237 at the portion where the bit contact holes 235 lie adjacent to each other becomes minimum. Consequently, it is essential that the short circuit between the bit lines 237 at the portion where the bit contact holes 235 lie adjacent to each other is completely avoided.
After that (though not shown), a second interlayer insulation film is formed on the overall surface of the substrate. After a node contact hole is formed which reaches the other of the N.sup.- -type source and drain region 214 through the BPSG film 233, the first and second silicon oxide films 221, 231 (and the gate insulation film 205), a storage node electrode is formed which is connected to the cell transistors via the node contact hole. Furthermore, a capacity insulation film, a cell plate electrode or the like are formed with the result that the DRAM is completed.
However, in the DRAM described above by referring to FIGS. 1A through 1D, FIG. 2A and FIG. 2B, there arises a disadvantage that the line width of the bit lines 237 in the peripheral circuit region 253 (particularly, in a portion located in the vicinity of the boundary region 252) becomes thinner than the line width in the cell array region 251 with the result that the bit lines are disconnected at this portion.
The wavelength .lambda. of the KrF excimer laser used in the exposure of the formation of the photoresist film pattern for the patterning of the bit lines 237 and the wiring 238 is 248 nm. The depth of focus (DOF) at the time of the exposure at 40 mJ is about 0.4 .mu.m. However, since the focus position is determined under the conditions described above, DOF/2=0.2 .mu.m comes to have an effective meaning. Consequently, in the case where the maximum step of the upper surface of the BPSG film 233 is larger than DOF/2=0.2 .mu.m, there is generated a portion where the photoresist film pattern is not formed. The maximum step of the upper surface of the BPSG film 233 is associated with the maximum step of the upper surface of the BPSG film 232. The maximum step of the upper surface of the BPSG film 232 is regulated by the sum of the thickness of the word lines 211 and the thickness of the first silicon oxide film 221. The sum is larger than the value of .lambda.. At the time of making fine the cell transistors, it is difficult to set the thickness of the word lines 211 in proportion to the reduction ratio.
When only the avoidance of the disconnection of the bit lines 237 is noted, only the exposure light amount may be reduced to about 36 mJ because the maximum step of the upper surface of the BPSG film 233 is about 270 nm. However, when such exposure light amount is reduced, the interval of the photoresist film patterns becomes narrow with the result that a short circuit is generated between the bit lines 237.